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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MPC2105C/D
512KB and 1MB BurstRAM Secondary Cache Modules for PowerPCTM PReP/CHRP Platforms
The MPC2105C and the MPC2106C are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The MPC2105C and MPC2106C utilize synchronous BurstRAMs. The modules are configured as 64K x 72, and 128K x 72 bits in a 178 (89 x 2) pin DIMM format. The MPC2105C uses four of the 3 V 64K x 18; the MPC2106C uses eight of the 3 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits is used. Bursts can be initiated with the ADS signal. Subsequent burst addresses are generated internal to the BurstRAM by the CNTEN signal. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control. Presence detect pins are available for auto configuration of the cache control. The module family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power savings. Both power supplies must be connected. All of these cache modules are plug and pin compatible with each other. * * * * * * * * * * * * * PowerPC-style Burst Counter on Chip Flow-Through Data I/O Plug and Pin Compatibility Multiple Clock Pins for Reduced Loading All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible Three State Outputs Byte Write Capability Fast Module Clock Rates: Up to 66 MHz Fast SRAM Access Times: 10 ns for Tag RAM Match 9 ns for Data RAM Decoupling Capacitors for Each Fast Static RAM High Quality Multi-Layer FR4 PWB With Separate Power and Ground Planes 178 Pin Card Edge Module Burndy Connector, Part Number: ELF178KSC-3Z50
MPC2105C MPC2106C
178-LEAD CARD EDGE TOP VIEW MPC2105C CASE 1132A-01 MPC2106C CASE 1132-01
1
24 25
47 48
89
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
10/14/97
(c) Motorola, Inc. 1997 MOTOROLA FAST SRAM
MPC2105C*MPC2106C 1
MPC2105C BLOCK DIAGRAM
VSS BA13 - BA28 69F618CTQ SA SBA ADSC DQA ADV SBB G DQB SE1 K 69F618CTQ SA ADSC ADV G SE1 SBA DQA SBB DQB K CWE2 DH16 - DH23 + DP2 CWE3 DH24 - DH31 + DP3 CLK0 CWE0 DH0 - DH7 + DP0 CWE1 DH8 - DH15 + DP1 CLK0 SRAM TIE OFF VDD '244 A13 - A28
ADS0 CNTEN0 CG0
SE2 SGW
SW ZZ
69F618CTQ SA ADSC ADV G SE1 SBA DQA SBB DQB K CWE4 DL0 - DL7 + DP4 CWE5 DL8 - DL15 + DP5 CLK1
ADSP
69F618CTQ SA ADSC ADV G SE1 SBA DQA SBB DQB K CWE6 DL16 - DL23 + DP6 CWE7 DL24 - DL31 + DP7 CLK1
A13 - A26 A1 - A12 TCLR TWE CLK2 MATCH DIRTYOUT VALIDIN DIRTYIN TG
TAG: 16K x 12 + V + D A0 - A13 TT1, WTD, E1 TAG0 -11 SFUNC, SG RESET TAH, TAG, TAD SW E2, PWRDN TW VCCQ K MATCH TA, VALIDQ WTQ DIRTYQ VALIDD VCC DIRTYD TG
VSS VCC via 100 VDD NC VCC
A0 CLK3 CLK4 ALE ADS1 CNTEN1 CG1 ADDR0 ADDR1 PD3
= NC = NC = NC = NC = NC = NC = NC = NC = NC J3
PD2 J2 PD1 J1 PD0
Note: BA28 is tied to SA0 on SRAM; BA27 is tied to SA1 on SRAM; STANDBY is tied to SE3 on SRAM.
J0
MPC2105C*MPC2106C 2
MOTOROLA FAST SRAM
MPC2106C BLOCK DIAGRAM
BA13 - BA28 BA12 69F618CTQ SA SBA ADSC DQA ADV SBB G DQB SE1 K 69F618CTQ SA ADSC ADV G SE1 SBA DQA SBB DQB K CWE2 DH16 - DH23 + DP2 CWE3 DH24 - DH31 + DP3 CLK1 69F618CTQ CWE0 DH0 - DH7 + DP0 CWE1 DH8 - DH15 + DP1 CLK0 SBB DQB SBA DQA K SA ADSC ADV G SE2 ADS1 CNTEN1 CG1 '244 A13 - A28 A12
ADS0 CNTEN0 CG0
69F618CTQ SBB DQB SBA DQA K SA ADSC ADV G SE2
69F618CTQ SA ADSC ADV G SE1 SBA DQA SBB DQB K CWE4 DL0 - DL7 + DP4 CWE5 DL8 - DL15 + DP5 CLK3
69F618CTQ SBB DQB SBA DQA K SA ADSC ADV G SE2
69F618CTQ SA ADSC ADV G SE1 SBA DQA SBB DQB K CWE6 DL16 - DL23 + DP6 CWE7 DL24 - DL31 + DP7 CLK4
69F618CTQ SBB DQB SBA DQA K SA ADSC ADV G SE2
BANK A: SE2 TIED TO. VDD VIA 100 .
BANK B: SE1 TIED TO. VSS SRAM TIE OFF
A13 - A26 A0 - A11 TCLR TWE CLK2 MATCH DIRTYOUT VALIDIN DIRTYIN TG
TAG: 16K x 12 + V + D V CC A0 - A13 TT1, WTD TAG0 -11 SFUNC, SG RESET TAH, TAG, TAD SW PWRDN TW VCCQ K MATCH TA, VALIDQ WTQ DIRTYQ VALIDD E1 DIRTYD E2 TG E1 E2
VCC VSS VCC via 100 VDD NC A12 VCC VSS A12 ALE ADDR0 ADDR1 PD3 SGW ADSP
VDD
SW ZZ
= NC = NC = NC J3
PD2 J2 Note: BA28 is tied to SA0 on SRAM; BA27 is tied to SA1 on SRAM; STANDBY is tied to SE3 on SRAM. PD1 J1 PD0 J0
MOTOROLA FAST SRAM
MPC2105C*MPC2106C 3
PIN ASSIGNMENT 178-LEAD DIMM TOP VIEW
VSS PD1/IDSDATA PD3 DH31 DH29 DH27 DH25 VDD CWE3 DH23 DH21 DH18 VSS DH16 CWE2 DH14 DH13 VCC DH10 DH8 CEW1 DH6 VDD DH4 VSS CLK0 VSS DH1 CWE0 DL31 DL30 VSS DL29 DL27 DL25 VCC CWE7 DL23 DL21 DL19 VSS DL17 CWE6 DL15 DL13 VSS DL10 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 016 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 VSS PD0/IDSCLK PD2 DH30 DH28 DH26 DH24 VDD DP3 DH22 DH20 DH19 VSS DH17 DP2 DH15 DH12 VCC DH11 DH9 DP1 DH7 VDD DH5 DH3 DH2 DH0 DP0 VSS CLK1 VSS DL28 DL26 DL24 DP7 VCC DL22 DL20 DL18 DL16 VSS DP6 DL14 DL12 DL11 VSS DL9 DL8 CWE5 DL6 VDD DL5 DL2 VSS CLK3 VSS CLK4 VSS CWE4 ALE VDD ADDR1 RESERVED CNTEN0 CNTEN1 A27 A24 A22 A20 VSS A18 A16 A15 A14 VDD A10 A8 A6 VSS A4 A2 A1 BURSTMODE VCC VALIDIN TWE STANDBY DIRTYOUT VSS 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 DP5 DL7 DL4 VDD DL3 DL1 DL0 VSS CLK2 VSS DP4 CG0 CG1 VDD ADDR0 RESERVED ADS0 ADS1 A28 A26 A25 A23 VSS A21 A19 A17 A13 VDD A12 A11 A9 VSS A7 A5 A3 A0 VCC TCLR MATCH TG DIRTYIN VSS
MPC2105C*MPC2106C 4
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations 66, 67, 68, 69, 71, 72, 73, 74, 76, 77, 78, 80, 81, 82, 83, 155, 156, 157, 158, 160, 161, 162, 163, 165, 166, 167, 169, 170, 171 62 151 64, 65 149 172 59, 60 30, 56, 115, 144, 146 153, 154 98, 104, 110, 118, 126, 132, 138, 148 4, 5, 6, 7, 10, 11, 12, 14, 16, 17, 19, 20, 22, 24, 25, 26, 27, 93, 94, 95, 96, 99, 100, 101, 103, 105, 106, 108, 109, 111, 113, 117 88 177 32, 33, 34, 37, 38, 39, 40, 43, 44, 45, 47, 49, 50, 52, 53, 54, 119, 120, 122, 123, 124, 127, 128, 129, 131, 133, 134, 136, 137, 139, 141, 142 9, 15, 21, 28, 35, 42, 48, 58 86 2 91 3, 92 63, 152 176 85 87 175 174 18, 36, 84, 107, 125, 173 8, 23, 51, 61, 75, 97, 112, 140, 150, 164 1, 13, 29, 31, 41, 46, 55, 57, 70, 79, 89, 90, 102, 114, 116, 121, 130, 135, 143, 145, 147, 159, 168, 178 Symbol A0 - A28 Type Input Description Address Inputs - (MSB:0, LSB:28).
ADDR0 ADDR1 ADS0, ADS1 ALE BURSTMODE CG0, CG1 CLK0 - CLK4 CNTEN0, CNTEN1 CWE0 - CWE7 DH0 - DH31
Input Input Input Input Input Input Input Input Input I/O
Least significant address bit when asynchronous Data RAMs are used. Next to least significant address bit when asynchronous Data RAMs are used. Data RAM Address Strobe - For MPC2105C use ADS0 only. For MPC2106C use ADS0, ADS1.. Data RAM Address Latch Enable - Use for asynchronous Data RAM only. Burstmode. 0 = Linear, 1 = Interleaved. Data RAM Output Enables. - For MPC2105C use CG0 only. For MPC2106C use CG0, CG1. Clock Inputs - CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for Data RAMs only. For MPC2106C use all the clocks. For MPC2105C use CLK0 - CLK2 only. Data RAM Count Enables - For MPC2105C use CNTEN0 only. For MPC2106C use CNTEN0, CNTEN1. Data RAM Write Enables - (MSB:0, LSB:7). High Data Bus - (MSB:0, LSB:31).
DIRTYIN DIRTYOUT DL0 - DL31
Input Output I/O
Dirty input bit. Dirty output bit. Low Data Bus - (MSB:0, LSB:31).
DP0 - DP7 MATCH PD0/IDSCLK PD1/IDSDATA PD2, PD3 RESERVED STANDBY TCLR TG TWE VALIDIN VCC VDD VSS
I/O Output Input I/O Output
Data Parity Bits - (MSB:0, LSB:7) Tag RAM active high match indication. Presence detect bit 0/EEPROM serial clock. (EEPROM option only). Presence detect bit 1/EEPROM serial data. (EEPROM option only). Presence detect bits. Reserved pin.
Input Input Input Input Input Input Input Input
Standby pin. Reduces standby power consumption. Tag RAM clear. Tag RAM output enable. Tag RAM write enable. Tag RAM valid bit. + 5 V power supply. Must be connected. + 3.3 V power supply. Must be connected. Ground.
MOTOROLA FAST SRAM
MPC2105C*MPC2106C 5
DATA RAM MCM69F618C SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
STANDBY H L L X X X X ADSx L L L H H H H CNTENx X X X L L H H CWEx X L H L H L H CLKx L-H L-H L-H L-H L-H L-H L-H Address Used N/A External Address External Address Next Address Next Address Current Address Current Address Operation Deselected Write Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst
NOTES: 1. X means don't care. 2. All inputs except CG must meet set-up and hold times for the low-to-high transition of clock (CLK0 - CLK4). 3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation Read Read Write Deselected CG L H X X I/O Status Data Out (DQ0 - DQ8) High-Z High-Z -- Data In High-Z
NOTES: 1. X means don't care. 2. For a write operation following a read operation, CG must be high before the input data required set-up time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating Power Supply Voltage Voltage Relative to VSS Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Data RAM Tag MPC2105C MPC2106C Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 30 20 4.6 9.2 - 10 to + 85 0 to +70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Storage Temperature Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
MPC2105C*MPC2106C 6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, VDD = 3.3 V 10%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VDD VIH VIL Min 4.75 3.00 2.2 - 0.5* Max 5.25 3.60 VDD + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns) for I 20.0 mA. ** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width 20 ns) for I 20.0 mA.
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VDD) Output Leakage Current (CG = VIH, Vout = 0 to VDD) TTL Output Low Voltage (IOL = + 8.0 mA) TTL Output High Voltage (IOH = - 4.0 mA) Data RAM Tag Data RAM Tag Symbol Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- 2.4 Max 1.0 5.0 1.0 5.0 0.4 -- Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Supply Current (CG = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time 20 ns) MPC2105C MPC2106C MPC2105C MPC2106C AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL or VIH VIL = 0.0 V and VIH 3.0 V, Cycle Time 20 ns) MPC2105C MPC2106C MPC2105C MPC2106C Symbol IDDA ICCA ISB1 (VDD) ISB1 (VCC) Max 900 1800 320 640 440 880 320 640 Unit mA mA mA mA
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance (A13 - A28) (Data RAM Control Pins) (CLK0 - CLK4) (Tag Control Pins) (MATCH, DIRTYOUT) (DH0 - DH31, DL0 - DL31) (A0 - A11) Symbol Cin Typ -- 16 8 -- -- 7 -- Max 15 24 12 5 10 9 10 Unit pF
Tag Output Capacitance Data RAM Input/Output Capacitance Tag Input/Output Capacitance
Cout CI/O CI/O
pF pF pF
MOTOROLA FAST SRAM
MPC2105C*MPC2106C 7
DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, VDD = 3.3 V 10% TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
MPC2105C MPC2106C Parameter Cycle Time Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Clock High Pulse Width Clock Low Pulse Width Setup Time Setup Times: Address Address Status Data In Write Address Advance Chip Enable Address Address Status Data In Write Address Advance Chip Enable Symbol tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tKHKL tKLKH tAVKH tSVKH tDVKH tWVKH tBAVVKH tEVKH tKHAX tKHTSX tKHDX tKHWX tKHBAX tKHEX Min 15 -- -- 6 3 0 2 -- 5 5 7.5 2.5 Max -- 9 5 -- -- -- 6 6 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 5, 6 5 4 Notes
Hold Times:
0.5
--
ns
5
NOTES: 1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW. 2. All read and write cycle timings are referenced from CLK or CG. 3. CG is a don't care when UW or LW is sampled low. 4. Maximum access times are guaranteed for all possible PowerPC external bus cycles. 5. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of CLK whenever TSP or TSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain enabled. 6. 5 ns of setup delay is incurred in address buffers.
MPC2105C*MPC2106C 8
MOTOROLA FAST SRAM
SYNCHRONOUS DATA RAM READ CYCLE
tKHKH CLK1, CLK0 tKLKH tKHKL
ADS0 tTSVKH tAVKH A(12, 13 - 26) (See Note 1) A1 tKHAX A2 tKHTSX
CWE0 - CWE7 tWVKH tEVKH STANDBY tKHEX tKHWX
tBAVKH CNTEN0 tKHQV tGLQV CG tGLQX tKHQX1 DATA OUT Q (A1) tGHQZ tKHQX2 Q (A2)
tKHBAX
tKHQV
tKHQZ
Q (A2 + 1)
Q (A2 + 2)
Q (A2 + 3)
READ
BURST READ
NOTES: 1. Cache addresses used are: 13 - 26 for MPC2105C; and 12 - 26 for MPC2106C. 2. Q1 (A2) represents the first ouput from the external address A2; Q2 (A2) represents the next output data in the burst sequence with A2 as the base address.
MOTOROLA FAST SRAM
MPC2105C*MPC2106C 9
SYNCHRONOUS DATA RAM WRITE CYCLE
tKHKH CLK1, CLK0 tKLKH tKHKL tSVKH ADS0 tKHTSX
tAVKH A(12, 13 - 26) A1
tKHAX
tAVKH A2
tKHAX
tWVKH CWE0 - CWE7
tKHWX
tEVKH STANDBY
tKHEX
tBAVKH CNTEN0
tKHBAX
tDVKH DATA IN D (A1) D (A2)
tKHDX D (A2 + 1) D (A2 + 2) D (A2 + 3)
SINGLE WRITE
BURST WRITE
NOTES: 1. Cache addresses used are: 13 - 26 for MPC2105C; and 12 - 26 for MPC2106C. 2. CG0 = VIH
MPC2105C*MPC2106C 10
MOTOROLA FAST SRAM
TAG RAM
RESET FUNCTION TRUTH TABLE (See Notes 1 and 2)
TCLR L L CLK L-H L-H TWE H L TAG0 - TAG11 High-Z -- DIRTYOUT L(3) -- MATCH L(3) -- Operation Reset Status Not Allowed POWER Active --
NOTES: 1. H = VIH, L = VIL, X = don`t care, -- = undefined. 2. TG is X for this table. 3. These are output states.
READ FUNCTION TRUTH TABLE (See Notes 1, 2, and 3)
TG L H TWE H X CLK X X TAG0 - TAG11 Dout High-Z VALIDIN -- -- DIRTYIN -- -- DIRTYOUT Dout -- MATCH Dout -- Operation Read Tag I/O Tag I/O Disable
WRITE FUNCTION TRUTH TABLE (See Notes 1 and 2)
TG H L TWE L L CLK L-H L-H TAG0 - TAG11 Din -- VALIDIN -- -- DIRTYIN -- -- DIRTYOUT -- -- MATCH L -- Operation Write Tag I/O Not Allowed
NOTES: 1. H = VIH, L = VIL, X = don`t care, -- = undefined. 2. This table applies when RESET and PWRDN are high. 3. Dout in this case is the same as Din. The input data is written through to the outputs during the write operation.
MATCH FUNCTION TRUTH TABLE (See Notes 1 through 4)
TG X L H H H TWE X H L H H TAG0 - TAG11 -- Dout Din TAGin TAGin VALIDIN(4) -- -- Din L H DIRTYIN(4) -- -- Din -- -- MATCH Dout L L L H Operation Selected Read Tag I/O Write Tag I/O, Status Bits Invalid Data - Dedicated Status Bits Match - Dedicated Status Bits
NOTES: 1. H = VIH, L = VIL, X = don`t care, -- = undefined. 2. M = high if TAGin equals the memory contents at the address; M = low if TAGin does not equal the contents at that address. 3. PWRDN and RESET are high for this table. GS and CLK are X. 4. This column represents the stored memory cell data for the given status bit at the selected address.
MOTOROLA FAST SRAM
MPC2105C*MPC2106C 11
TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
TAG RAM READ CYCLE (See Notes 1 through 4)
Tag RAM Parameter Clock Access Time Output Enable to Output Valid Output Enable to Output Active Output Disable to Q High-Z Status Bit Hold from Address Change Address Access Time Status Bits Tag Bit Hold from Address Change Address Access Time Tag Bits Symbol tKHQV tGLQV tGLQX tGHQZ tAXSX tAVSV tAVQX tAVQV Min -- -- 0 1 3 -- 3 -- Max 10 8 -- 6 -- 10 -- 12 Unit ns ns ns ns ns ns ns ns
NOTES: 1. Setup and hold times, W (write) refers to TWE. 2. A read cycle is defined by TWE high. A write cycle is defined by TWE low. 3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles. 4. Tag reads are asynchronous.
TAG RAM WRITE CYCLE (See Notes 1 through 4)
Tag RAM Parameter Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock High to Output Active Setup Times Hold Times Status Output Hold Clock High to Status Bits Valid Address Write Address Write Symbol tKHKH tKHKL tKLKH tKHQX tAVKH tWVKH tKHAX tKHWX tKHSX tKHSV Min 15 4.5 4.5 1.5 Max -- -- -- -- Unit ns ns ns ns
3 1.5
0 --
-- --
-- 9
ns ns
ns ns
NOTES: 1. Setup and hold times, W (write) refers to TWE. 2. A read cycle is defined by TWE high. A write cycle is defined by TWE low. 3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles. 4. Tag writes are synchronous.
MPC2105C*MPC2106C 12
MOTOROLA FAST SRAM
TAG RAM WRITE AND READ CYCLES (See Note 2)
STATUS WRITE TAG WRITE TAG READ AFTER WRITE TAG READ AFTER READ
CLK t KLKH t KHKH
MOTOROLA FAST SRAM
VALID t AVKH t WVKH t KHWX t KHAX VALID VALID t AVQV t AXQX t WVKH t KHQV t KHQX (See Note 1) t GHQZ (See Note 1) t KHWX t GLQV t GLQX t AVKH VALID INPUT t AVSV t WVKH VALID t KHSV t KHSX VALID VALID VALID t KHWX t AXSX t KHAX VALID OUTPUT VALID OUTPUT t AVSV t AXSX
t KHKL
A(12, 13,-26 (See Note 3)
TWE
TG
A0 - A11
VALID OUTPUT
VALIDIN DIRTYIN
DIRTYOUT
VALID
MPC2105C*MPC2106C 13
NOTES: 1. Transition is measured plus or minus 200 mV from steady state. 2. TCLR = High. 3. Cache addresses used are: A13 - A26 for MPC2105C, A12 - A26 for MPC2106C.
TAG RAM MATCH CYCLE
Tag RAM Parameter Clock High Write to MATCH Invalid Clock High Read to MATCH Valid Address Valid to MATCH Valid MATCH Valid Hold from Address Change TG Low to MATCH Invalid TG High to MATCH Valid Symbol tKHML tKHMV tAVMV tAXMX tGLML tGHMX Min -- -- -- 2 -- -- Max 7 10 10 -- 7 8 Unit ns ns ns ns ns ns
TAG RAM RESET (TCLR) CYCLE
Tag RAM Parameter TCLR Setup Time TCLR Hold Time Status Bit Reset Time Status Bit Hold from TCLR Low TCLR Low to MATCH Invalid TCLR High to MATCH Valid TCLR Low to TAG High-Z TCLR High to TAG Active STANDBY Setup to TCLR Low TCLR High to TWE Low Symbol tSTC tHTC tSRST tSHRS tRSML tRSMV tRSQZ tRSQX tPDSR tRHWX Min 4 1 -- 2 -- -- -- -- 30 80 Max -- -- 60 -- 10 100 10 100 -- -- Unit ns ns ns ns ns ns ns ns ns ns
TIMING LIMITS
Z0 = 50 OUTPUT 50 VL = 1.5 V The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1. AC Test Load
MPC2105C*MPC2106C 14
MOTOROLA FAST SRAM
TAG RAM MATCH CYCLE
MOTOROLA FAST SRAM
VALID ADDRESS VALID MATCH DATA FROM: PROCESSOR t WVKH t KHWX t KHWX t WVKH t WVKH TAG RAM PROCESSOR t GLML t KHML MATCH VALID t KHMV VALID VALID t GLMX
CLK
A(12, 13 - 26*
t AVMV t AXMX
A0 - A11
TWE
TG
MATCH
VALID
MPC2105C*MPC2106C 15
* Cache addresses used are: A13 - A26 for MPC2105C, A12 - A26 for MPC2106C.
TAG RAM TCLR FUNCTION
CLK tSTC TCLR tSHRS DIRTYOUT tWVKH TWE tRHWX tSRST tHTC
tRSMV MATCH tRSQZ* A0 - A11 * Transition is measured plus or minus 200 mV from steady state. tRSQX VALID
ORDERING INFORMATION (Order by Full Part Number) MPC
Motorola Memory Prefix Part Number
210xC
XX
XX
Speed (66 = 66 MHz) Package (DG = Gold Pad DIMM)
Full Part Numbers -- MPC2105CDG66 MPC2106CDG66
MPC2105C = 512KB, synchronous MPC2106C = 1MB, synchronous
MPC2105C*MPC2106C 16
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
178 LEAD CARD EDGE MPC2105C CASE 1132A-01
D 0.006
2X M
BCA
L
D1
A
2X
A1
B VIEW A
2X
D2
MOTOROLA FAST SRAM
EEEEEEEEEEEEE EEEEEEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEEE EE EEEE EE EEEE EE EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE
COMPONENT AREA
24 25 1 47 48 89
C L
E
A5
NOTE 4
A
R D6
R
E1
NOTE 5
D5
VIEW A D7 0.006 M C B A D4
E2 0.016 C SIDE VIEW
M NOTES 3 AND 6
L
D3
FRONT VIEW
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN INCHES. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS E AND A5 DEFINE A DOUBLE-SIDED MODULE. 5. DIMENSION E1 DEFINES OPTIONAL SINGLE-SIDED MODULE. 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. INCHES MIN MAX 1.190 1.210 0.545 --- 0.095 --- --- 0.010 0.195 --- 0.195 --- 0.039 0.043 5.055 5.065 0.100 --- 0.190 --- 1.255 1.265 3.405 3.410 1.250 BSC 0.072 0.076 0.075 0.081 0.050 BSC 0.075 BSC --- 0.210 --- 0.140 0.055 0.070
90
178
EE EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEE EEEEEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE E E EEEE EEEEEEE
COMPONENT AREA
BACK VIEW
C L
1
47
48
A4
A2 A3
178X
0.006
L
b CBA
L
4X 86X
e1 e
VIEW A
DIM A A1 A2 A3 A4 A5 b D D1 D2 D3 D4 D5 D6 D7 e e1 E E1 E2
EEEEEE E EEEE EE EEEEEE E EEEE E EEEEEE EEEEE
MPC2105C*MPC2106C 17
178 LEAD CARD EDGE MPC2106C CASE 1132-01 D 0.006
2X M
BCA
L
A
2X
A1
B VIEW A
2X
D2
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; SPD, Strategic Planning Office; 4-32-1, Nishi-Gotanda; Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488
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MPC2105C*MPC2106C 18
EEEEEEEEEEEE EEEE E EEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE E EEEEEEEEEEEEE EEEEEEEEEEEE EEEE E EEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE E EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE
COMPONENT AREA
1 24 25 47 48 89
D1
C L
E
A5
NOTE 4
A
R D6
R
E1
NOTE 5
D5
VIEW A D7 0.006 M C B A D4
E2 0.016 C SIDE VIEW
M NOTES 3 AND 6
L
D3
FRONT VIEW
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN INCHES. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS E AND A5 DEFINE A DOUBLE-SIDED MODULE. 5. DIMENSION E1 DEFINES OPTIONAL SINGLE-SIDED MODULE. 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. INCHES MIN MAX 1.390 1.410 0.545 --- 0.095 --- --- 0.010 0.195 --- 0.195 --- 0.039 0.043 5.055 5.065 0.100 --- 0.190 --- 1.255 1.265 3.405 3.410 1.250 BSC 0.072 0.076 0.075 0.081 0.050 BSC 0.075 BSC --- 0.210 --- 0.140 0.055 0.070
E EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEE EE EEEE EE EEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE E EEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEE EEEEEEEEE EE EEEE EE EEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE E
90 178
COMPONENT AREA
BACK VIEW
C L
1
47
48
A4
A2 A3
178X
0.006
L
b CBA
L
4X 86X
e1 e
VIEW A
DIM A A1 A2 A3 A4 A5 b D D1 D2 D3 D4 D5 D6 D7 e e1 E E1 E2
E EEE E EE EEEEEE EEEEEE EEEEEE EE EEEEE
MPC2105C/D MOTOROLA FAST SRAM

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